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CPU RISC-V

RISC-V std review Note 3

Memory Model

Still figuire out what this acutally doing.

hart

  • Hardware thread
  • Own user register state(?What?)

FENCE

  • Type I
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|31-28|27|26|25|24|23|22|21|20|19-15|14-12|11-7|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|    0|PI|PO|PR|PW|SI|SO|SR|SW|  rs1|func3|  rd|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

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