Categories
CPU Digital Design RISC-V

RISC-V std review Note 1

RISC-V

This is the notes for reviewing riscv-spec-v2.2.pdf
– no branch delay slots
– optional variable-length instruction encoding

instruction set

  • characterized by width of integer registers
Instruction set integer width (bit)
RV32x 32
RV64x 64
suffix meaning
I basic integer operation
M integer multiplication and division
A atmoic read, modify and write memory
F single-precision floating-point
D double-precision floating-point
G general-purpose scalar intsruction (IMAFD)
  • fixed-length 32-bit instructions must aligned on 32-bit boundaries
  • variable-length instructions align on 16-bit
  • compressed 16-bit instructions allow aligned on 16-bit

Instruction Length Encoding

+---------+---------+------------+------------+
| Length  | offset  |     byte 0 |     byte 1 |
+---------+---------+------------+------------+
|  16 bit |         | 0bxxxxxx00 | 0bxxxxxxxx |
|         |         | 0bxxxxxx01 | 0bxxxxxxxx |
|         |         | 0bxxxxxx10 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  32 bit |         | 0bxxx00011 | 0bxxxxxxxx |
|         |         | 0bxxx00111 | 0bxxxxxxxx |
|         |         | 0bxxx01011 | 0bxxxxxxxx |
|         |         | 0bxxx01111 | 0bxxxxxxxx |
|         |         | 0bxxx10011 | 0bxxxxxxxx |
|         |         | 0bxxx10111 | 0bxxxxxxxx |
|         |         | 0bxxx11011 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  48 bit |         | 0bxx011111 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  64 bit |         | 0bx0111111 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  80 bit |         | 0bx1111111 | 0bx000xxxx |
+---------+---------+------------+------------|
|  96 bit |         | 0bx1111111 | 0bx001xxxx |
+---------+---------+------------+------------|
| 112 bit |         | 0bx1111111 | 0bx010xxxx |
+---------+---------+------------+------------|
| 128 bit |         | 0bx1111111 | 0bx011xxxx |
+---------+---------+------------+------------|

Leave a Reply

Your email address will not be published. Required fields are marked *