Memory Model

Still figuire out what this acutally doing.

hart

• Hardware thread
• Own user register state(?What?)

FENCE

• Type I

+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|31-28|27|26|25|24|23|22|21|20|19-15|14-12|11-7|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|    0|PI|PO|PR|PW|SI|SO|SR|SW|  rs1|func3|  rd|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

RISC-V

This is the notes for reviewing riscv-spec-v2.2.pdf (part 2)
– 31 general-purpose register x1-x32
– x0 as constant 0
– register width == RV”XX” a.k.a RV32I = 32 bit register

• pc (program counter)

base ISA

4 code instruction formats (R/I/S/U)

instruction format

immediate always sign-extended

rd  = Destination Register
rs? = Source Register
+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+
| type |      31 |  30 - 25 | 24 - 21 |      20 | 19 - 15 | 14 - 12 |   11 - 8 |       7 |  6 - 0 |
+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+
|    R |              func7 |               rs2 |     rs1 |   func3 |                 rd | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    I |                              imm[11:0] |     rs1 |   func3 |                 rd | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    S |          imm[11:5] |               rs2 |     rs1 |   func3 |           imm[4:0] | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    B | imm[12] |imm[11:5] |               rs2 |     rs1 |   func3 | imm[4:0] | imm[11] | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    U |                                                 imm[31:12] |                 rd | opcode |
+------+---------+--------------------+---------+---------+---------+----------+---------+--------+
|    J | imm[20] |          imm[10:1] | imm[11] |        imm[19:12] |                 rd | opcode |
+------+---------+--------------------+---------+---------+---------+----------+---------+--------+

immediate format

Not understanmd Figure 2.4

+------+----------+-------------+-------------+----------+-------------+-------------+----------+
| type |       31 |     30 - 20 |     19 - 12 |       11 |     10 -  5 |       4 - 1 |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    I |                                        inst[31] | inst[30:25] | inst[24:21] | inst[20] |
+------+-------------------------------------------------+-------------+-------------+----------+
|    S |                                        inst[31] | inst[30:25] | inst[11: 8] | inst[ 7] |
+------+--------------------------------------+----------+-------------+-------------+----------+
|    B |                             inst[31] | inst[ 7] | inst[30:25] | inst[11: 8] |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    U | inst[31] |               inst[30:12] |                                               0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    J |             | inst[31] | inst[19:12] | inst[20] | inst[30:25] | inst[24:21] |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+

integer computational instrucitons

Integer Register-Immediate Instructions

Type I

• ADDI rd, rs1, I => rd = rs1 + I
  • ADDI rd, rs1, 0 => MV rd, rs1
• SLTI rd, rs1, I => rd = rs1 < I
• SLTIU rd, rs1, I => rd = rs1 < I (as UINT)
  • SLTIU rd, rs1, 1 => SEQZ rd, rs => rd = rs == 0
• ANDI rd, rs1, I => rd = rs1 & I (as INT)
• AND rd, rs1, I => rd = rs1 & I (as UINT)
• ORI rd, rs1, I => rd = rs1 | I (as INT)
• OR rd, rs1, I => rd = rs1 | I (as UINT)
• XORI rd, rs1, I => rd = rs1 & I (as INT)
  XORI rd, rs1, -1 => NOT rd, rs1
• XOR rd, rs1, I => rd = rs1 & I (as UINT)
• SLLI rd, rs1, I[4:0] => rd = rs1 << I
• SRLI rd, rs1, I[4:0] => rd = rs1 >> I (logical)
• SRAI rd, rs1, I[4:0] => rd = rs1 >>> I (arithmetical) *I[11:5]==0b0100000

Type U

• LUI rd, I => rd = {I[31:12],12’h000}
• AUIPC rd, I => rd = {I[31:12],12’h000} + PC
  • AUIPC rd, 0 => rd = PC

Integer Register-Register Operations

Type R

• ADD rd, rs1, rs2 => rd = rs1 + rs2
• SLT rd, rs1, rs2 => rd = rs1 < rs2
• SLTU rd, rs1, rs2 => rd = rs1 < rs2 (as UINT)
• AND rd, rs1, rs2 => rd = rs1 & rs2
• OR rd, rs1, rs2 => rd = rs1 | rs2
• XOR rd, rs1, rs2 => rd = rs1 ^ rs2
• SLL rd, rs1, rs2 => rd = rs1 << rs2
• SRL rd, rs1, rs2 => rd = rs1 >> rs2
• SUB rd, rs1, rs2 => rd = rs1 – rs2
• SRA rd, rs1, rs2 => rd = rs1 >>> rs2
  SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in
register rs1 by the shift amount held in the lower 5 bits of register rs2.

NOP Instruction

• NOP = ADDI x0,x0,0

Control Transfer Instructions

Unconditional Jumps

Type J

• JAL rd, I => rd = PC + 4; PC = PC + I[20:1]<<1
  • JAL x0, I => J I = PC = PC + I[20:1]<<1

Type I

• JALR rd, rs1, I => temp = (rs1 + I[11:0]) & -2; rd = PC + 4; PC = PC + temp
  **** Misalignment may generate when JAL&JALR is not align 32 bit boundary

Conditional branch

Type B

• BEQ rs1, rs2, I => PC = (rs1 == rs2) ? PC+I : PC+4
• BEQ rs1, rs2, I => PC = (rs1 != rs2) ? PC+I : PC+4
• BLT rs1, rs2, I => PC = (rs1 < rs2) ? PC+I : PC+4
• BLTU rs1, rs2, I => PC = (rs1 < rs2) ? PC+I : PC+4 (as UINT)
• BGE rs1, rs2, I => PC = (rs1 >= rs2) ? PC+I : PC+4
• BGEU rs1, rs2, I => PC = (rs1 >= rs2) ? PC+I : PC+4 (as UINT)

Load and Store Instructions

• LOAD(LW/LH/LHU/LB/LBU)
• L* rd, rs, I => rd = ((U)Int32)(*(TYPE*)(rs+I))
• STORE rs1, rs2, I => *(rs1+I) = rs2