RISC-V std review Note 3

By yaus on June 16, 2018June 16, 2018Leave a Comment

Memory Model

Still figuire out what this acutally doing.

hart

Hardware thread
Own user register state(?What?)

FENCE

Type I

+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|31-28|27|26|25|24|23|22|21|20|19-15|14-12|11-7|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+
|    0|PI|PO|PR|PW|SI|SO|SR|SW|  rs1|func3|  rd|6-0|
+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

|31-28|27|26|25|24|23|22|21|20|19-15|14-12|11-7|6-0|

+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

| 0|PI|PO|PR|PW|SI|SO|SR|SW| rs1|func3| rd|6-0|

+-----+--+--+--+--+--+--+--+--+-----+-----+----+---+

RISC-V std review Note 2

By yaus on June 11, 2018June 16, 2018Leave a Comment

RISC-V

This is the notes for reviewing riscv-spec-v2.2.pdf (part 2)
– 31 general-purpose register x1-x32
– x0 as constant 0
– register width == RV”XX” a.k.a RV32I = 32 bit register

pc (program counter)

base ISA

4 code instruction formats (R/I/S/U)

instruction format

immediate always sign-extended

rd  = Destination Register
rs? = Source Register
+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+
| type |      31 |  30 - 25 | 24 - 21 |      20 | 19 - 15 | 14 - 12 |   11 - 8 |       7 |  6 - 0 |
+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+
|    R |              func7 |               rs2 |     rs1 |   func3 |                 rd | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    I |                              imm[11:0] |     rs1 |   func3 |                 rd | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    S |          imm[11:5] |               rs2 |     rs1 |   func3 |           imm[4:0] | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    B | imm[12] |imm[11:5] |               rs2 |     rs1 |   func3 | imm[4:0] | imm[11] | opcode |
+------+---------+----------+---------+-------------------+---------+----------+---------+--------+
|    U |                                                 imm[31:12] |                 rd | opcode |
+------+---------+--------------------+---------+---------+---------+----------+---------+--------+
|    J | imm[20] |          imm[10:1] | imm[11] |        imm[19:12] |                 rd | opcode |
+------+---------+--------------------+---------+---------+---------+----------+---------+--------+

rd = Destination Register

rs? = Source Register

+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+

| type | 31 | 30 - 25 | 24 - 21 | 20 | 19 - 15 | 14 - 12 | 11 - 8 | 7 | 6 - 0 |

+------+---------+----------+---------+---------+---------+---------+----------+---------+--------+

| R | func7 | rs2 | rs1 | func3 | rd | opcode |

+------+---------+----------+---------+-------------------+---------+----------+---------+--------+

| I | imm[11:0] | rs1 | func3 | rd | opcode |

+------+---------+----------+---------+-------------------+---------+----------+---------+--------+

| S | imm[11:5] | rs2 | rs1 | func3 | imm[4:0] | opcode |

+------+---------+----------+---------+-------------------+---------+----------+---------+--------+

| B | imm[12] |imm[11:5] | rs2 | rs1 | func3 | imm[4:0] | imm[11] | opcode |

+------+---------+----------+---------+-------------------+---------+----------+---------+--------+

| U | imm[31:12] | rd | opcode |

+------+---------+--------------------+---------+---------+---------+----------+---------+--------+

| J | imm[20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode |

+------+---------+--------------------+---------+---------+---------+----------+---------+--------+

immediate format

Not understanmd Figure 2.4

+------+----------+-------------+-------------+----------+-------------+-------------+----------+
| type |       31 |     30 - 20 |     19 - 12 |       11 |     10 -  5 |       4 - 1 |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    I |                                        inst[31] | inst[30:25] | inst[24:21] | inst[20] |
+------+-------------------------------------------------+-------------+-------------+----------+
|    S |                                        inst[31] | inst[30:25] | inst[11: 8] | inst[ 7] |
+------+--------------------------------------+----------+-------------+-------------+----------+
|    B |                             inst[31] | inst[ 7] | inst[30:25] | inst[11: 8] |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    U | inst[31] |               inst[30:12] |                                               0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+
|    J |             | inst[31] | inst[19:12] | inst[20] | inst[30:25] | inst[24:21] |        0 |
+------+----------+-------------+-------------+----------+-------------+-------------+----------+

+------+----------+-------------+-------------+----------+-------------+-------------+----------+

| type | 31 | 30 - 20 | 19 - 12 | 11 | 10 - 5 | 4 - 1 | 0 |

+------+----------+-------------+-------------+----------+-------------+-------------+----------+

+------+-------------------------------------------------+-------------+-------------+----------+

+------+--------------------------------------+----------+-------------+-------------+----------+

+------+----------+-------------+-------------+----------+-------------+-------------+----------+

| U | inst[31] | inst[30:12] | 0 |

+------+----------+-------------+-------------+----------+-------------+-------------+----------+

+------+----------+-------------+-------------+----------+-------------+-------------+----------+

integer computational instrucitons

Integer Register-Immediate Instructions

Type I

ADDI rd, rs1, I => rd = rs1 + I
- ADDI rd, rs1, 0 => MV rd, rs1
SLTI rd, rs1, I => rd = rs1 < I
SLTIU rd, rs1, I => rd = rs1 < I (as UINT)
- SLTIU rd, rs1, 1 => SEQZ rd, rs => rd = rs == 0
ANDI rd, rs1, I => rd = rs1 & I (as INT)
AND rd, rs1, I => rd = rs1 & I (as UINT)
ORI rd, rs1, I => rd = rs1 | I (as INT)
OR rd, rs1, I => rd = rs1 | I (as UINT)
XORI rd, rs1, I => rd = rs1 & I (as INT)
XORI rd, rs1, -1 => NOT rd, rs1
XOR rd, rs1, I => rd = rs1 & I (as UINT)
SLLI rd, rs1, I[4:0] => rd = rs1 << I
SRLI rd, rs1, I[4:0] => rd = rs1 >> I (logical)
SRAI rd, rs1, I[4:0] => rd = rs1 >>> I (arithmetical) *I[11:5]==0b0100000

Type U

LUI rd, I => rd = {I[31:12],12’h000}
AUIPC rd, I => rd = {I[31:12],12’h000} + PC
- AUIPC rd, 0 => rd = PC

Integer Register-Register Operations

Type R

ADD rd, rs1, rs2 => rd = rs1 + rs2
SLT rd, rs1, rs2 => rd = rs1 < rs2
SLTU rd, rs1, rs2 => rd = rs1 < rs2 (as UINT)
AND rd, rs1, rs2 => rd = rs1 & rs2
OR rd, rs1, rs2 => rd = rs1 | rs2
XOR rd, rs1, rs2 => rd = rs1 ^ rs2
SLL rd, rs1, rs2 => rd = rs1 << rs2
SRL rd, rs1, rs2 => rd = rs1 >> rs2
SUB rd, rs1, rs2 => rd = rs1 – rs2
SRA rd, rs1, rs2 => rd = rs1 >>> rs2
SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

NOP Instruction

NOP = ADDI x0,x0,0

Control Transfer Instructions

Unconditional Jumps

Type J

JAL rd, I => rd = PC + 4; PC = PC + I[20:1]<<1
- JAL x0, I => J I = PC = PC + I[20:1]<<1

Type I

JALR rd, rs1, I => temp = (rs1 + I[11:0]) & -2; rd = PC + 4; PC = PC + temp
**** Misalignment may generate when JAL&JALR is not align 32 bit boundary

Conditional branch

Type B

BEQ rs1, rs2, I => PC = (rs1 == rs2) ? PC+I : PC+4
BEQ rs1, rs2, I => PC = (rs1 != rs2) ? PC+I : PC+4
BLT rs1, rs2, I => PC = (rs1 < rs2) ? PC+I : PC+4
BLTU rs1, rs2, I => PC = (rs1 < rs2) ? PC+I : PC+4 (as UINT)
BGE rs1, rs2, I => PC = (rs1 >= rs2) ? PC+I : PC+4
BGEU rs1, rs2, I => PC = (rs1 >= rs2) ? PC+I : PC+4 (as UINT)

Load and Store Instructions

LOAD(LW/LH/LHU/LB/LBU)
L* rd, rs, I => rd = ((U)Int32)(*(TYPE*)(rs+I))
STORE rs1, rs2, I => *(rs1+I) = rs2

RISC-V std review Note 1

By yaus on June 10, 2018June 11, 2018Leave a Comment

RISC-V

This is the notes for reviewing riscv-spec-v2.2.pdf
– no branch delay slots
– optional variable-length instruction encoding

instruction set

characterized by width of integer registers

Instruction set	integer width (bit)
RV32x	32
RV64x	64

suffix	meaning
I	basic integer operation
M	integer multiplication and division
A	atmoic read, modify and write memory
F	single-precision floating-point
D	double-precision floating-point
G	general-purpose scalar intsruction (IMAFD)

fixed-length 32-bit instructions must aligned on 32-bit boundaries
variable-length instructions align on 16-bit
compressed 16-bit instructions allow aligned on 16-bit

Instruction Length Encoding

+---------+---------+------------+------------+
| Length  | offset  |     byte 0 |     byte 1 |
+---------+---------+------------+------------+
|  16 bit |         | 0bxxxxxx00 | 0bxxxxxxxx |
|         |         | 0bxxxxxx01 | 0bxxxxxxxx |
|         |         | 0bxxxxxx10 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  32 bit |         | 0bxxx00011 | 0bxxxxxxxx |
|         |         | 0bxxx00111 | 0bxxxxxxxx |
|         |         | 0bxxx01011 | 0bxxxxxxxx |
|         |         | 0bxxx01111 | 0bxxxxxxxx |
|         |         | 0bxxx10011 | 0bxxxxxxxx |
|         |         | 0bxxx10111 | 0bxxxxxxxx |
|         |         | 0bxxx11011 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  48 bit |         | 0bxx011111 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  64 bit |         | 0bx0111111 | 0bxxxxxxxx |
+---------+---------+------------+------------|
|  80 bit |         | 0bx1111111 | 0bx000xxxx |
+---------+---------+------------+------------|
|  96 bit |         | 0bx1111111 | 0bx001xxxx |
+---------+---------+------------+------------|
| 112 bit |         | 0bx1111111 | 0bx010xxxx |
+---------+---------+------------+------------|
| 128 bit |         | 0bx1111111 | 0bx011xxxx |
+---------+---------+------------+------------|

+---------+---------+------------+------------+

+---------+---------+------------+------------+

+---------+---------+------------+------------|

+---------+---------+------------+------------|

| 48 bit | | 0bxx011111 | 0bxxxxxxxx |

+---------+---------+------------+------------|

| 64 bit | | 0bx0111111 | 0bxxxxxxxx |

+---------+---------+------------+------------|

| 80 bit | | 0bx1111111 | 0bx000xxxx |

+---------+---------+------------+------------|

| 96 bit | | 0bx1111111 | 0bx001xxxx |

+---------+---------+------------+------------|

| 112 bit | | 0bx1111111 | 0bx010xxxx |

+---------+---------+------------+------------|

| 128 bit | | 0bx1111111 | 0bx011xxxx |

+---------+---------+------------+------------|

Digital Logic 101.1: Numeric System

By yaus on June 13, 2017December 11, 2017Leave a Comment

Base 10 (a.k.a. decimal) is the numeric system which most people using in daily life.

For the digital logic or computer system in nowadays, it would use binary instead. Binary only have two values, 0 and 1. For any number that larger than one, it should be represented by two digital.

$2_{10} = 10_2$
$5_{10} = 101_2$

A number represented as binary has longer length comparing with decimal. Usually, hexadecimal is used for written down in the program.

$1_{10} = 1_{2} = 1_{16}$
$2_{10} = 10_{2} = 2_{16}$
$3_{10} = 11_{2} = 3_{16}$
$4_{10} = 100_{2} = 4_{16}$
$5_{10} = 101_{2} = 5_{16}$
$6_{10} = 110_{2} = 6_{16}$
$7_{10} = 111_{2} = 7_{16}$
$8_{10} = 1000_{2} = 8_{16}$
$9_{10} = 1001_{2} = 9_{16}$
$10_{10} = 1010_{2} = A_{16}$
$11_{10} = 1011_{2} = B_{16}$
$12_{10} = 1100_{2} = C_{16}$
$13_{10} = 1101_{2} = D_{16}$
$14_{10} = 1110_{2} = E_{16}$
$15_{10} = 1111_{2} = F_{16}$
$16_{10} = 10000_{2} = 10_{16}$

Prefixes is add for represent the binary and hexadecimal in the source code. Here is the example in C.
0x0A

Starting a project for FEC

By yaus on March 15, 2017March 15, 2017Leave a Comment

Here is the github link.

It is a open source project to modeling the forward error correction coding with Python.

I hope I would complete it.

New Domain

By yaus on March 5, 2017March 5, 2017Leave a Comment

I got a new domain! yaus.hk

[Unboxing]EVGA SuperNova 1000T2

By yaus on September 1, 2016Leave a Comment

_MG_1648

_MG_1650

_MG_1649

_MG_1651 _MG_1654 _MG_1653

_MG_1656

[Unboxing] Intel Core i7 6900k + ASUS ROG Strix X99 + H115I

By yaus on July 6, 2016September 1, 2016Leave a Comment

IMG_20160622_212311 — Group photo for all new items

Component List of PC

Intel Core i7 6900K
ASUS ROG STRIX X99 Gaming
Corsair Vengeance LPX DDR4-3000 16GB Kit (8GB×2) ×2
Inno3D iChill GeForce GTX 970 4GB Ultra
Plextor M5S 256GB
Toshiba 4TB
Corsair CX600M
Thermaltake Suppressor F51

IMG_20160622_224721 — Content inside Mainboard’s BOX

IMG_20160623_012431

A bundle of wire.

Capture2

It is seems that I7-6900K is very power-demanded CPU. A 280mm AIO water cooling system is not enough to suppress the heat generation of i7-6900K.

Next generartion VR/AR display

By yaus on May 12, 2016May 13, 2016Leave a Comment

What will be the next generation VR?

4K? No. UHD only is enhacement of existing VR. The product existing in market focus on user head orientation. This is the first generation.

The next focus will be the human vision system. When we see, our eyeballs would point to object with different angle. Seen existing products provide the best visual in the center of screen. Any other angle of view would be strange. It is because the vision model is not able to handle this. I propose VR display require to add eyetracking modules for eyeballs movement compensation or view reconstruction.

Keil 5 Create Project

By yaus on November 3, 2015November 3, 2015Leave a Comment

For creating a project, select Project -> New µVision Project in menu.

Then, select the directory path for storage of project.

After choosing the project path, a window for selecting MCU model will popup.

Type in the model number that you’re using. If it don’t show the model you want, please double check you have install the device package in CMSIS pack installer.

The package icon show green that means the device package had been installed.