RISC-V std review Note 1


This is the notes for reviewing riscv-spec-v2.2.pdf
– no branch delay slots
– optional variable-length instruction encoding

instruction set

  • characterized by width of integer registers
Instruction set integer width (bit)
RV32x 32
RV64x 64
suffix meaning
I basic integer operation
M integer multiplication and division
A atmoic read, modify and write memory
F single-precision floating-point
D double-precision floating-point
G general-purpose scalar intsruction (IMAFD)
  • fixed-length 32-bit instructions must aligned on 32-bit boundaries
  • variable-length instructions align on 16-bit
  • compressed 16-bit instructions allow aligned on 16-bit

Instruction Length Encoding

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